FPGA & Digital Design Engineer · EPFL
Master student in Computer Science at EPFL, specialising in digital design and FPGA development. Currently seeking an internship in hardware design, verification, or embedded systems for Summer 2026.
Semester project verifying a Flash Controller on a Xilinx FPGA for the open-source X-HEEP RISC-V MCU. Designed a Write-Back Cache (1–4 sectors) in SystemVerilog to optimise memory access latency. Used Integrated Logic Analyzers (ILA) to debug hardware/software issues across I/O operations, and developed C test applications and TCL-automated QuestaSim simulations to stress-test the controller.
Implemented and evaluated a Linux kernel eBPF extension to customize page cache eviction and admission policies for application-specific memory constraints, directly manipulating kernel data structures and synchronization primitives.
Designed a ring-buffer architecture enabling asynchronous I/O page-fault handling for an IOMMU, eliminating performance bottlenecks caused by synchronous DMA blocking and static memory pinning. Built on the Midgard intermediate address-space framework.
Developed a custom RTL hardware accelerator from scratch on the Gecko 5 Education Board FPGA to offload graphical rendering from the CPU. Achieved a 50× speedup over the software baseline by profiling C code to identify critical paths and designing optimised pipelined RTL.
Conducted remote side-channel power analysis on multi-tenant FPGAs using voltage-routing delay sensors to capture power consumption traces during partial reconfiguration. Analysed attacker/victim placement impact on leakage in a dynamic partial reconfiguration environment.
Designed and implemented a cycle-accurate simulator modelling the microarchitecture of a MIPS R10000 out-of-order processor, incorporating pipeline stages, register renaming, reorder buffer management, and exception handling.
Developed a multiplayer “Overcooked”-style cooking game on the Nintendo DS in bare-metal C. Implemented sprite rendering, tile-based collision detection, and networked multiplayer over DS WiFi, while optimising RAM usage and handling real-time constraints on resource-limited hardware.
Developed embedded firmware to interface an Arduino Nano 33 IoT with a FlexiForce load-cell sensor and HX711 amplifier. Programmed custom logic to trigger micro-vibrators based on real-time weight thresholds, with a Blynk mobile GUI for remote monitoring and configuration over WiFi.